Bus driving circuit and memory device having same

ABSTRACT

A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a bus driving circuitfor driving a bus line provided in a large scale integrated circuit.More specifically, the invention relates to a bus driving circuit usedfor transferring output data from a pre-charge type circuit via a busline.

[0003] 2. Description of the Prior Art

[0004] In recent years, large scale integrated circuits (LSIs) arelarge-scaled and accelerated at a request for the advance of the finepatterning technology and the improvement of the system performance.

[0005] As microprocessors, LSIs having a plurality of circuit blockstherein have a bus line for connecting these circuit blocks.

[0006] For example, as shown in FIG. 3, a large memory unit 30 built ina microprocessor is separated into a plurality of memory blocks 30 ₁, 30₂, 30 ₃ and 30 ₄ by addresses. The data output terminals of these memoryblocks are connected to a bus line 10 via a read circuit 32 and a busdriving circuit 40. Such a bus line 10 is driven by the bus drivingcircuit 40 of an activated one of the memory blocks to transfer data tothe next stage circuit.

[0007]FIG. 4 shows a conventional bus driving circuit. This bus drivingcircuit 40A comprises: a tristate buffer 44 comprising a P-channelMOSFET 44 a and an N-channel MOSFET 44 b; and a gate control circuit 42for controlling the gate of each of the MOSFETs of the tristate buffer44 on the basis of an enable signal and input data.

[0008] The gate control circuit 42 comprises an AND gate 42 a, aninverter 42 b and an OR gate 42 c. The AND gate 42 a performs an ANDoperation on the basis of the enable signal and the input data totransmit the operated results to the gate of the N-channel MOSFET 44 b.The OR gate 42 c performs an OR operation on the basis of the input dataand a signal produced by inverting the enable signal by the inverter 42b, to transmit the operated results to the gate of the P-channel MOSFET44 a. Furthermore, the input data are produced in synchronism with aclock signal. The output of the tristate buffer 44 is connected to thebus line 10.

[0009] The operation of the bus driving circuit 40A is as follows. Whenthe enable signal is inactive, the output of the tristate buffer 44 hashigh impedance so as not to drive the bus line 10. At this time, if thebus driving circuit 40A is connected to one memory block of the memoryunit 30 shown in FIG. 3, other memory blocks are activated, and otherbus driving circuits connected to the activated memory blocks drive thebus line 10 to perform data transfer.

[0010] On the other hand, if the enable signal inputted to the busdriving circuit 40A is activated, the bus line 10 is driven inaccordance with the input data to perform data transfer as shown in FIG.5. Furthermore, as shown in FIG. 4, an inverter 50 and a latch circuit60 controlled by a clock signal CK are provided on the next stagecircuit side, to which data are transferred. The potential of the busline 10 holds data until the next memory access is started (until theclock signal CK is raised next time) (see FIG. 5)

[0011]FIG. 6 shows another example of a conventional bus drivingcircuit. In a bus driving circuit 40B shown in FIG. 6, the gate controlcircuit 42 of the bus driving circuit 40A shown in FIG. 4 is replacedwith a gate control circuit 43. The gate control circuit 43 comprises anAND gate 43 a. The AND gate 43 a performs an AND operation on the basisof input data and an enable signal to transmit the operated results tothe gate of an N-channel MOSFET 44 b of a tristate buffer 44.Furthermore, to the gate of a P-channel MOSFET 44 a of the tristatebuffer 44, an inverted signal /PC of a pre-charge signal PC synchronizedwith a clock signal is inputted.

[0012] The conventional bus driving circuit 40B shown in FIG. 6 isdesigned to receive, as data input, the output of a pre-charge typecircuit, i.e., a circuit wherein its output is previously set at a lowpotential and wherein the data transition of the output occurs only whena high potential is outputted. Furthermore, a read circuit 32 forreading data from the memory unit 30 shown in FIG. 3 is a pre-chargetype circuit.

[0013] Referring to FIG. 7, the operation of the bus driving circuit40B, which is shown in FIG. 6 and which is applied to the memory unit30, will be described below.

[0014] The bus driving circuit 40B turns the P-channel MOSFET 44 a ON,in response to the pre-charge signal PC during a memory access, topreviously set the bus line 10 at the high potential. Thereafter,although the MOSFET 44 a is turned OFF, the bus line is held to be thehigh potential by a latch circuit 70. Furthermore, the latch circuit 70is provided on the side of a circuit, to which data are transferred. Insuch a state, if the enable signal is activated and if high potentialdata are outputted from the read circuit 32 of the memory unit 30, theN-channel MOSFET 44 b is turned ON, so that the bus line 10 is driven ata low potential to perform data transfer (see FIG. 7). The potential ofthe bus line 10 is held by the latch circuit 70 even after the memoryaccess ends to set the output of the read circuit 32 at a low potentialagain until the next memory access is started to pre-charge the bus line10 by the pre-charge signal /PC (see FIG. 7)

[0015] As described above, the potential of the bus line 10 connected tothe conventional bus driving circuit 40B shown in FIG. 6 is held by thelatch circuit 70 until the bus line 10 is pre-charged by the pre-chargesignal /PC even after the memory access ends to set the output of theread circuit 32 at the low potential again. Therefore, since it is notrequired to provide the latch circuit 60 for operating in response tothe clock signal, which is provided at the next stage of the bus line 10as shown in FIG. 4, the number of gate stages can be smaller than thatof the bus driving circuit 40A shown in FIG. 4, and the data transfercan be rapidly carried out.

[0016] However, the bus driving circuit shown in FIG. 6 is weak innoises since the bus line 10 remains being held at the high potential bythe latch circuit 70 having a weak driving force when the output of theread circuit 32 has a low potential. In particular, the bus lines 10 arearranged in parallel at a long distance, and the data transitions occursimultaneously, so that there is much noise due to the coupling capacitywith the next line.

[0017] Therefore, if the next bus line is driven at the low potential,there is some possibility that the potential of the bus line to be heldat the high potential changes to the low potential under the influenceof the coupling capacity to cause malfunction.

SUMMARY OF THE INVENTION

[0018] It is therefore an object of the present invention to eliminatethe aforementioned problems and to provide a bus driving circuit capableof inhibiting the influence of the coupling noises between bus lines andof rapidly transferring data.

[0019] In order to accomplish the aforementioned and other objects,according to one aspect of the present invention, a bus driving circuitcomprises: bus pre-charge means for pre-charging a bus line on the basisof a pre-charge signal produced in synchronism with a clock signal; atristate buffer for driving the bus line on the basis of a gate controlsignal; and a gate control circuit for transmitting the gate controlsignal to the tristate buffer so as not to drive the bus line when anenable signal is in an inactive state, and for transmitting the gatecontrol signal to the tristate buffer so as to drive the but line on thebasis of the potential of the bus line and data inputted from apre-charge type circuit when the enable signal is in an active state.

[0020] The gate control circuit may output first and second gate controlsignals, and the tristate buffer may comprise: a first MOSFET of a firstconductive type, which has a source connected to a first power supply, agate for receiving the first gate control signal, and a drain connectedto the bus line; and a second MOSFET of a second conductive typedifferent from the first conductive type, the second MOSFET having asource connected to a second power supply for supplying a lowerpotential than that of the first power supply, a gate for receiving thesecond gate control signal, and a drain connected to the drain of thefirst MOSFET, the first MOSFET being turned ON only when the potentialof the bus line is a logical value “H”.

[0021] The bus pre-charge means may hold the input data on the bus lineby pre-charging the bus line only during an access operation for thepre-charge circuit.

[0022] The gate control circuit may comprise: an AND gate for performingan AND operation on the basis of the enable signal and the input data tooutput the second gate control signal; a NAND gate for performing a NANDoperation on the basis of the enable signal and the potential of the busline; and an OR gate for performing an OR operation on the basis of theinput data and the output of the NAND gate to output the first gatecontrol signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be understood more fully from thedetailed description given herebelow and from the accompanying drawingsof the preferred embodiments of the invention. However, the drawings arenot intended to imply limitation of the invention to a specificembodiment, but are for explanation and understanding only.

[0024] In the drawings:

[0025]FIG. 1 is a block diagram of a preferred embodiment of a busdriving circuit according to the present invention;

[0026]FIG. 2 is a timing chart for explaining the operation of thepreferred embodiment shown in FIG. 1;

[0027]FIG. 3 is a block diagram of a memory unit;

[0028]FIG. 4 is a circuit diagram of a conventional bus driving circuit;

[0029]FIG. 5 is a timing chart for explaining the operation of the busdriving circuit shown in FIG. 4;

[0030]FIG. 6 is a circuit diagram of another example of a conventionalbus driving circuit;

[0031]FIG. 7 is a timing chart for explaining the operation of the busdriving circuit shown in FIG. 6;

[0032]FIG. 8 is a block diagram of another preferred embodiment of a busdriving circuit according to the present invention;

[0033]FIG. 9 is a block diagram of a preferred embodiment of a memoryunit according to the present invention; and

[0034]FIG. 10 is a timing chart for explaining the operation of thememory unit shown in FIG. 9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035]FIG. 1 shows a preferred embodiment of a bus driving circuitaccording to the present invention. In this preferred embodiment, a busdriving circuit 1 is designed to transfer data, which are outputted froma pre-charge type circuit (e.g., a read circuit 32 of a memory unit 30shown in FIG. 3), by driving a bus line 10. The bus driving circuit 1comprises a gate control circuit 2, a tristate buffer 4, and a buspre-charge means 6.

[0036] The tristate buffer 4 comprises a P-channel MOSFET 4 a and anN-channel MOSFET 4 b. The source of the MOSFET 4 a is connected to afirst power supply, and the drain thereof is connected to the drain ofthe MOSFET 4 b and the bus line 10. The source of the MOSFET 4 b isconnected to a second power supply having a lower power supply potentialthan that of the first power supply.

[0037] The gate control circuit 2 is designed to drive the bus line 10by controlling the gates of the MOSFETS 4 a and 4 b constituting thetristate buffer on the basis of input data, which are transmitted fromthe pre-charge type circuit, an enable signal and the potential of thebus line 10. The gate control circuit 2 comprises an AND gate 2 a, aNAND gate 2 b and an OR gate 2 c. The AND gate 2 a performs an ANDoperation on the basis of the input data and the enable signal totransmit the operated results to the gate of the N-channel MOSFET 4 b ofthe tristate buffer 4. The NAND gate 2 b performs a NAND operation onthe basis of the enable signal and the potential of the bus line 10. TheOR gate 2 c performs an OR operation on the basis of the input data andthe output of the NAND gate to transmit the operated results to the gateof the P-channel MOSFET of the tristate buffer 4.

[0038] The bus pre-charge means 6 comprises a P-channel MOSFET 6 a. Thesource of the MOSFET 6 a is connected to the first power supply, and thedrain thereof is connected to the bus line 10. The gate of the MOSFET 6a receives an inverted signal /PC of a pre-charge signal PC.Furthermore, the pre-charge signal PC is activated in synchronism with aclock signal CK, and the pre-charge signal PC is inactive before theinput data are transmitted to the bus driving circuit 1.

[0039] A latch circuit 70 is connected to the bus line 10. The latchcircuit 70 is provided on the side of a circuit (not shown), to whichdata are transferred via the bus line 10.

[0040] Referring to FIG. 2, when the bus driving circuit 1 in thispreferred embodiment receives, as input data, the output of the memoryunit for reading data in synchronism with a clock signal, the operationof the bus driving circuit 1 will be described below.

[0041] The memory unit performs a memory access using a leading edge ofa clock as a trigger, and the data output (i.e., the input data of thebus driving circuit 1) is previously set at an “L” level to perform adata transition in accordance with read data. After the data read ends,the data output is set at the “L” level again. Because the read circuitof a typical memory unit is a pre-charge type circuit which is operatedusing a pulse signal produced from a clock. Therefore, a waveform shownin FIG. 2 is given to the input of the bus driving circuit 1 from thememory unit.

[0042] The bus line 10 is set at an “H” level by the bus pre-chargemeans 6 during the data output (an access period) from the leading edgeof a clock signal CK, at which a memory access is carried out (see FIG.2). When the enable signal has the “L” level, the potentials of the “H”and “L” levels are applied to the MOSFETs 4 a and 4 b of the tristatebuffer 4, respectively, so that the tristate buffer 4 does not drive thebus line 10. When the enable signal has the “H” level and when the busdriving circuit 1 is activated, an “L” level signal is inputted to thegate terminal of the N-channel MOSFET 4 b since the input data has the“L” level, and an “L” level signal is inputted to the gate terminal ofthe P-channel MOSFET 4 a since the potential of the bus line 10 has the“H” level and since the input data have the “L” level. Thus, the busdriving circuit 1 drives the bus line 10 at the “H” level (see FIG. 2)

[0043] Then, when the bus pre-charge means 6 is deactivated and when amemory access is carried out to apply the “H” level to the input signal(input data) of the bus driving circuit 1, both of the gate terminals ofthe P-channel MOSFET 4 a and N-channel MOSFET 4 b of the tristate buffer4 have the “H” level, so that the bus line 10 is driven at the “L”level. At this time, since the data bus line 10 has the “L” level, the“H” level is applied to the gate terminal of the P-channel MOSFET 4 a ofthe tristate buffer 4 regardless of the state of other signals.Therefore, after the memory access ends, when the data input levelchanges to the “L” level again, the “L” level of the bus line 10 is heldby the latch circuit 70 while both of the N-channel MOSFET 4 b andP-channel MOSFET 4 a of the tristate buffer 4 are turned OFF. Data areheld until the pre-charge of the bus line 10 is carried out after thenext memory access is started, so that it is not required to provide thelatch circuit 60 based on the clock as shown in FIG. 4. Thus, it ispossible to reduce the number of gate stages, and it is possible torapidly transfer data.

[0044] In addition, when the output of the memory circuit has the “L”level, the P-channel MOSFET 4 a of the bus driving circuit 1 is in ONstate to continuously drive the data bus at the “H” level, so that it ispossible to prevent malfunction due to the coupling noises of theadjacent data bus lines.

[0045] Furthermore, while the bus line 10 has been pre-charged in theabove described preferred embodiment, the bus line 10 may be discharged.FIG. 8 shows a bus driving circuit 1A in this case. The P-channelMOSFETs 4 a and 6 a shown in FIG. 1 are replaced with N-channel MOSFETs4 c and 6 c, respectively. The N-channel MOSFET 4 b, the AND gate 2 a,the NAND gate 2 b and the OR gate are replaced with a P-channel MOSFET 4d, a NOR gate 2 d, a NOR gate 2 e, and an AND gate 2 f, respectively(see FIG. 8). In addition, the input data of the bus driving circuit arepreviously set at the “H” level.

[0046] Referring to FIGS. 9 and 10, a memory unit having the bus drivingcircuit in the preferred embodiment shown in FIG. 1 will be describedbelow. FIG. 9 is a block diagram of the memory unit, and FIG. 10 is atiming chart showing the operation of the memory unit.

[0047] As shown in FIG. 9, the memory unit 30 comprises a plurality ofmemory cells 30 a ₁, 30 a ₂ arranged in the form of a matrix, word linesWL₁, WL₂ for selecting memory cells on the same line, a pair of bitlines BL, /BL for transmitting the potential levels of the memory cellsselected by the word lines, a pre-charge circuit 31 for pre-charging thepotentials of the pair of bit lines at the “H” level, and a senseamplifier circuit (which will be hereinafter referred to as an S/Acircuit) 32 for amplifying the potentials of the memory cells which areread to the pair of bit lines. The output of the S/A circuit 32, i.e.,the output of the memory unit 30, is supplied to the bus driving circuit1 as input data.

[0048] Referring to FIG. 10, the operation of the memory unit 30 will bedescribed below.

[0049] The potentials of the pair of bit lines BL, /BL are set at the“H” level by the pre-charge circuit 31. At this time, for example, ifthe word line WL₁ is activated, the pre-charge circuit 31 is turned OFF,and the memory cell holding data of the “L” level (e.g., the memory cell30A₁) drives the bit line BL or /BL so that the potential of the bitline BL is the “L” level. At this time, the data transition of the bitline BL or /BL is very slow since a small memory cell drives the bitline BL or /BL, to which a plurality of memory cells are connected andto which a heavy load is applied. Therefore, the S/A circuit 32 is usedfor amplifying the potential of the bit line.

[0050] The S/A circuit 32 amplifies the potential of the bit line BL or/BL in timing with the input of an S/A enable signal. After the wordline is activated, the S/A enable signal is activated in a certaintiming, so that the S/A circuit 32 amplifies the very small potentialsof the pair of bit lines BL, /BL to a CMOS level potential to outputdata of the selected memory cell to the outside, i.e., to the busdriving circuit 1.

[0051] After the data are read, the S/A circuit 32 is deactivated, andthe potentials of the pair of bit lines BL, /BL are pre-charged to the“H” level again by the pre-charge circuit 32 for the next readoperation.

[0052] Thus, in order for the memory unit 30 to carry out a memoryaccess (a data read operation) and a pre-charge operation in one clockcycle, a potential (an initial value) during the pre-charge operation isfirst outputted as the output data of the memory unit 30. Therefore,after the memory access, required data are outputted to the bus drivingcircuit 1, and the pre-charge operation is carried out by the pre-chargecircuit 31 again, so that the initial value is outputted.

[0053] As described above, according to the present invention, it ispossible to inhibit the influence of the coupling noises between buslines, and it is possible to rapidly transfer data.

[0054] While the present invention has been disclosed in terms of thepreferred embodiment in order to facilitate better understandingthereof, it should be appreciated that the invention can be embodied invarious ways without departing from the principle of the invention.Therefore, the invention should be understood to include all possibleembodiments and modification to the shown embodiments which can beembodied without departing from the principle of the invention as setforth in the appended claims.

What is claim is:
 1. A bus driving circuit comprising: bus pre-chargemeans for pre-charging a bus line on the basis of a pre-charge signalproduced in synchronism with a clock signal; a tristate buffer fordriving said bus line on the basis of a gate control signal; and a gatecontrol circuit for transmitting said gate control signal to saidtristate buffer so as not to drive said bus line when an enable signalis in an inactive state, and for transmitting said gate control signalto said tristate buffer so as to drive said but line on the basis of thepotential of said bus line and data inputted from a pre-charge typecircuit when said enable signal is in an active state.
 2. A bus drivingcircuit as set forth in claim 1, wherein said gate control circuitoutputs first and second gate control signals, and said tristate buffercomprises: a first MOSFET of a first conductive type, which has a sourceconnected to a first power supply, a gate for receiving said first gatecontrol signal, and a drain connected to said bus line; and a secondMOSFET of a second conductive type different from said first conductivetype, said second MOSFET having a source connected to a second powersupply for supplying a lower potential than that of said first powersupply, a gate for receiving said second gate control signal, and adrain connected to said drain of said first MOSFET, said first MOSFETbeing turned ON only when the potential of said bus line is a logicalvalue “H”.
 3. A bus driving circuit as set forth in claim 1, whereinsaid bus pre-charge means holds said input data on said bus line bypre-charging said bus line only during an access operation for saidpre-charge circuit.
 4. A bus driving circuit as set forth in claim 2,wherein said first MOSFET is a P-channel MOSFET, and said second MOSFETis an N-channel MOSFET.
 5. A bus driving circuit as set forth in claim4, wherein said gate control circuit comprises: an AND gate forperforming an AND operation on the basis of said enable signal and saidinput data to output said second gate control signal; a NAND gate forperforming a NAND operation on the basis of said enable signal and thepotential of said bus line; and an OR gate for performing an ORoperation on the basis of said input data and the output of said NANDgate to output said first gate control signal.
 6. A bus driving circuitas set forth in claim 5, wherein said bus pre-charge means is aP-channel MOSFET.
 7. A bus driving circuit as set forth in claim 6,wherein a latch circuit is connected to said bus line.
 8. A bus drivingcircuit as set forth in claim 2, wherein said first MOSFET is anN-channel MOSFET, and said second MOSFET is a P-channel MOSFET.
 9. A busdriving circuit as set forth in claim 8, wherein said gate controlcircuit comprises: an OR gate for performing an OR operation on thebasis of said enable signal and said input data to output said secondgate control signal; a NOR gate for performing a NOR operation on thebasis of said enable signal and the potential of said bus line; and anAND gate for performing an AND operation on the basis of said input dataand the output of said NOR gate to output said first gate controlsignal.
 10. A bus driving circuit as set forth in claim 9, wherein saidbus pre-charge means is an N-channel MOSFET.
 11. A memory unitcomprising: a plurality of memory cells arranged in the form of amatrix; word lines for selecting memory cells on the same line; bitlines for transmitting the potential levels of the memory cells selectedby said word lines; a bit line pre-charge circuit for pre-charging saidbit lines; a sense amplifier circuit for amplifying the potentials ofthe memory cells which are read to said bit lines; bus pre-charge meansfor pre-charging a bus line on the basis of a pre-charge signal producedin synchronism with a clock signal; a tristate buffer for driving saidbus line on the basis of a gate control signal; and a gate controlcircuit for transmitting said gate control signal to said tristatebuffer so as not to drive said bus line when an enable signal is in aninactive state, and for transmitting said gate control signal to saidtristate buffer so as to drive said bus line on the basis of thepotential of said bus line and the output data of said sense amplifiercircuit when said enable signal is in an active state.
 12. A memory unitas set forth in claim 11, wherein said gate control circuit outputsfirst and second gate control signals, and said tristate buffercomprises: a first MOSFET of a first conductive type, which has a sourceconnected to a first power supply, a gate for receiving said first gatecontrol signal, and a drain connected to said bus line; and a secondMOSFET of a second conductive type different from said first conductivetype, said second MOSFET having a source connected to a second powersupply for supplying a lower potential than that of said first powersupply, a gate for receiving said second gate control signal, and adrain connected to said drain of said first MOSFET, said first MOSFETbeing turned ON only when the potential of said bus line is a logicalvalue “H”.
 13. A bus driving circuit as set forth in claim 11, whereinsaid bus pre-charge means holds said input data on said bus line bypre-charging said bus line only during an access operation for saidpre-charge circuit.
 14. A bus driving circuit as set forth in claim 12,wherein said first MOSFET is a P-channel MOSFET, and said second MOSFETis an N-channel MOSFET.
 15. A bus driving circuit as set forth in claim14, wherein said gate control circuit comprises: an AND gate forperforming an AND operation on the basis of said enable signal and saidinput data to output said second gate control signal; a NAND gate forperforming a NAND operation on the basis of said enable signal and thepotential of said bus line; and an OR gate for performing an ORoperation on the basis of said input data and the output of said NANDgate to output said first gate control signal.
 16. A bus driving circuitas set forth in claim 15, wherein said bus pre-charge means is aP-channel MOSFET.